[{"data":1,"prerenderedAt":990},["ShallowReactive",2],{"search-index":3,"doc-plat-porting-checklist-bootloader-kernel-rootfs-2026":101},[4,8,12,17,21,25,29,33,37,42,47,52,57,62,67,72,77,82,87,92,97],{"_path":5,"title":6,"description":7},"/dev/eu-cyber-resilience-act-firmware-evidence-pack","Eu Cyber Resilience Act Firmware Evidence Pack","title: \"EU Cyber Resilience Act in Practice for Firmware Teams: Engineering Tasks and Evidence Pack\"\ndescription: \"Practical breakdown of the EU Cyber Resilience Act requirements for embedded firmware teams, covering technical obligations, SBOM requirements, vulnerability handling, and the evidence pack needed for compliance.\"\ndate: 2026-04-19T08:00:00Z\nlastmod: 2026-04-19T08:00:00Z\ndraft: false\nhero: \"/images/hero/eu-cyber-resilience-act-firmware-evidence-pack-1600x900.jpg\"\ntags:",{"_path":9,"title":10,"description":11},"/dev/pkg/firmware-sboms-spdx-cyclonedx-2026","Firmware Sboms Spdx Cyclonedx 2026","title: \"Firmware SBOMs in 2026: SPDX vs CycloneDX, What to Publish, and What to Automate\"\ndescription: \"Practical comparison of SPDX and CycloneDX for firmware SBOMs, covering what to include, automation approaches, tooling, and publication strategies for embedded Linux products.\"\ndate: 2026-04-19T08:00:00Z\nlastmod: 2026-04-19T08:00:00Z\ndraft: false\nhero: \"/images/hero/firmware-sboms-spdx-cyclonedx-2026-1600x900.jpg\"\ntags:",{"_path":13,"title":14,"description":15,"date":16},"/dev/pkg/spdx-3-0-embedded-builds-practical","SPDX 3.0 for Embedded Builds: Packages, Files, and Relationships Engineers Actually Use","Practical guide to SPDX 3.0 for embedded Linux, covering the data model, package and file elements, relationship types, and how to produce useful SPDX documents from Yocto and Buildroot builds.","2026-04-19T08:00:00Z",{"_path":18,"title":19,"description":20},"/dev/slsa-build-provenance-firmware-sign-verify","Slsa Build Provenance Firmware Sign Verify","title: \"SLSA Build Provenance for Firmware: What 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BitBake builds.\"\ndate: 2026-04-11T07:09:00Z\nlastmod: 2026-04-11T07:09:00Z\ndraft: false\nhero: \"/images/hero/yocto-esdk-faster-iteration-2026-1600x900.jpg\"\ntags:",{"_path":34,"title":35,"description":36},"/dev/yocto-layers-maintainable-strategy-2026","Yocto Layers Maintainable Strategy 2026","title: \"Yocto Layers That Stay Maintainable: Layer Model, Naming, and Upgrade Strategy (2026)\"\ndescription: \"Practical guidance on structuring Yocto layers for long-term maintainability, covering layer boundaries, naming conventions, version pinning, and upgrade workflows.\"\ndate: 2026-04-07T13:41:00Z\nlastmod: 2026-04-07T13:41:00Z\ndraft: false\nhero: \"/images/hero/yocto-layers-maintainable-strategy-2026-1600x900.jpg\"\ntags:",{"_path":38,"title":39,"description":40,"date":41},"/doc/bootlin-toolchains-arm-riscv-2026","Bootlin Toolchains in Practice: Picking the Right Prebuilt Toolchain for ARM and RISC-V","How to select and validate Bootlin prebuilt cross-compilation toolchains for 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targets.","2026-03-14T06:29:00Z",{"_path":93,"title":94,"description":95,"date":96},"/doc/verified-boot-patterns-uboot-keys-failure-modes","Verified Boot Patterns in U-Boot: What to Verify, Where Keys Live, and Failure Modes","Deep dive into U-Boot verified boot patterns covering signature scopes, key storage options, common failure modes, and practical debugging techniques for embedded Linux platforms.","2026-03-16T18:11:00Z",{"_path":98,"title":99,"description":100},"/image-manifest","ProteanOS Image Manifest","This document lists all hero and supporting images needed for the website.",{"_path":68,"_dir":102,"_draft":103,"_partial":103,"_locale":104,"title":69,"description":70,"date":71,"lastmod":71,"draft":103,"hero":105,"tags":106,"category":110,"body":111,"_type":984,"_id":985,"_source":986,"_file":987,"_stem":988,"_extension":989},"plat",false,"","/images/hero/porting-checklist-bootloader-kernel-rootfs-2026-1600x900.jpg",[107,108,109],"Embedded Linux","ProteanOS","Porting","doc-plat",{"type":112,"children":113,"toc":941},"root",[114,122,129,136,161,167,172,177,183,189,194,229,234,240,245,307,312,318,323,328,346,351,357,362,370,375,381,386,394,400,406,411,417,422,428,433,439,503,508,514,520,533,566,572,577,585,590,596,622,632,642,648,653,686,691,697,703,708,716,721,727,732,740,746,767,773,786,792,798,811,817,830,836,841,847,853,858,889,895,900,906,911,917,922,935],{"type":115,"tag":116,"props":117,"children":118},"element","p",{},[119],{"type":120,"value":121},"text","Porting embedded Linux to a new board follows a predictable sequence: get the bootloader running, boot a kernel, mount a root filesystem. Each stage has specific checkpoints and failure modes. This checklist distills the process into verifiable steps, based on practical experience bringing up ARM and RISC-V boards.",{"type":115,"tag":123,"props":124,"children":126},"h2",{"id":125},"before-you-start",[127],{"type":120,"value":128},"Before you start",{"type":115,"tag":130,"props":131,"children":133},"h3",{"id":132},"gather-documentation",[134],{"type":120,"value":135},"Gather documentation",{"type":115,"tag":137,"props":138,"children":139},"ul",{},[140,146,151,156],{"type":115,"tag":141,"props":142,"children":143},"li",{},[144],{"type":120,"value":145},"SoC technical reference manual (TRM) — the essential document",{"type":115,"tag":141,"props":147,"children":148},{},[149],{"type":120,"value":150},"Board schematics — for pin muxing and peripheral connections",{"type":115,"tag":141,"props":152,"children":153},{},[154],{"type":120,"value":155},"SoC errata sheet — known silicon bugs that affect boot or driver behaviour",{"type":115,"tag":141,"props":157,"children":158},{},[159],{"type":120,"value":160},"Vendor BSP (if available) — even if you don't use it directly, it shows what works",{"type":115,"tag":130,"props":162,"children":164},{"id":163},"set-up-serial-console",[165],{"type":120,"value":166},"Set up serial console",{"type":115,"tag":116,"props":168,"children":169},{},[170],{"type":120,"value":171},"You cannot debug boot problems without a serial console. Identify the debug UART on the schematic, connect a USB-to-UART adapter, and verify you can see characters at the correct baud rate (usually 115200).",{"type":115,"tag":116,"props":173,"children":174},{},[175],{"type":120,"value":176},"This is step zero. Everything else depends on it.",{"type":115,"tag":123,"props":178,"children":180},{"id":179},"stage-1-bootloader",[181],{"type":120,"value":182},"Stage 1: Bootloader",{"type":115,"tag":130,"props":184,"children":186},{"id":185},"_11-identify-the-boot-flow",[187],{"type":120,"value":188},"1.1 Identify the boot flow",{"type":115,"tag":116,"props":190,"children":191},{},[192],{"type":120,"value":193},"Most modern SoCs use a multi-stage boot:",{"type":115,"tag":195,"props":196,"children":197},"ol",{},[198,209,219],{"type":115,"tag":141,"props":199,"children":200},{},[201,207],{"type":115,"tag":202,"props":203,"children":204},"strong",{},[205],{"type":120,"value":206},"ROM bootloader",{"type":120,"value":208}," (in silicon) — loads SPL/TPL from boot media",{"type":115,"tag":141,"props":210,"children":211},{},[212,217],{"type":115,"tag":202,"props":213,"children":214},{},[215],{"type":120,"value":216},"SPL (Secondary Program Loader)",{"type":120,"value":218}," — initializes DRAM, loads U-Boot",{"type":115,"tag":141,"props":220,"children":221},{},[222,227],{"type":115,"tag":202,"props":223,"children":224},{},[225],{"type":120,"value":226},"U-Boot",{"type":120,"value":228}," — loads kernel, DTB, and optional initramfs",{"type":115,"tag":116,"props":230,"children":231},{},[232],{"type":120,"value":233},"Determine what the ROM expects: which boot media (eMMC, SPI NOR, SD card), what image format, what header structure.",{"type":115,"tag":130,"props":235,"children":237},{"id":236},"_12-build-u-boot-spl-u-boot-proper",[238],{"type":120,"value":239},"1.2 Build U-Boot SPL + U-Boot proper",{"type":115,"tag":116,"props":241,"children":242},{},[243],{"type":120,"value":244},"Start with the vendor's defconfig if available. If not, find the closest supported board in mainline U-Boot and adapt.",{"type":115,"tag":246,"props":247,"children":251},"pre",{"code":248,"language":249,"meta":104,"className":250,"style":104},"make CROSS_COMPILE=aarch64-linux- vendor_board_defconfig\nmake CROSS_COMPILE=aarch64-linux- -j$(nproc)\n","bash","language-bash shiki shiki-themes github-dark",[252],{"type":115,"tag":253,"props":254,"children":255},"code",{"__ignoreMap":104},[256,279],{"type":115,"tag":257,"props":258,"children":261},"span",{"class":259,"line":260},"line",1,[262,268,274],{"type":115,"tag":257,"props":263,"children":265},{"style":264},"--shiki-default:#B392F0",[266],{"type":120,"value":267},"make",{"type":115,"tag":257,"props":269,"children":271},{"style":270},"--shiki-default:#9ECBFF",[272],{"type":120,"value":273}," CROSS_COMPILE=aarch64-linux-",{"type":115,"tag":257,"props":275,"children":276},{"style":270},[277],{"type":120,"value":278}," vendor_board_defconfig\n",{"type":115,"tag":257,"props":280,"children":282},{"class":259,"line":281},2,[283,287,291,297,302],{"type":115,"tag":257,"props":284,"children":285},{"style":264},[286],{"type":120,"value":267},{"type":115,"tag":257,"props":288,"children":289},{"style":270},[290],{"type":120,"value":273},{"type":115,"tag":257,"props":292,"children":294},{"style":293},"--shiki-default:#79B8FF",[295],{"type":120,"value":296}," -j$(",{"type":115,"tag":257,"props":298,"children":299},{"style":264},[300],{"type":120,"value":301},"nproc",{"type":115,"tag":257,"props":303,"children":304},{"style":293},[305],{"type":120,"value":306},")\n",{"type":115,"tag":116,"props":308,"children":309},{},[310],{"type":120,"value":311},"Checkpoint: U-Boot prints its banner on the serial console and reaches the command prompt.",{"type":115,"tag":130,"props":313,"children":315},{"id":314},"_13-dram-initialization",[316],{"type":120,"value":317},"1.3 DRAM initialization",{"type":115,"tag":116,"props":319,"children":320},{},[321],{"type":120,"value":322},"DRAM initialization is the most common failure point in bootloader bring-up. Symptoms: hang during SPL, garbled output, or random crashes.",{"type":115,"tag":116,"props":324,"children":325},{},[326],{"type":120,"value":327},"Verify:",{"type":115,"tag":137,"props":329,"children":330},{},[331,336,341],{"type":115,"tag":141,"props":332,"children":333},{},[334],{"type":120,"value":335},"DDR timing parameters match the actual DRAM chips on the board",{"type":115,"tag":141,"props":337,"children":338},{},[339],{"type":120,"value":340},"Voltage rail for DRAM is correct and stable",{"type":115,"tag":141,"props":342,"children":343},{},[344],{"type":120,"value":345},"If the SoC has a DDR PHY training sequence, verify it completes",{"type":115,"tag":116,"props":347,"children":348},{},[349],{"type":120,"value":350},"If using vendor-provided DRAM initialization blobs, ensure the blob matches the board's DRAM configuration (density, speed grade, topology).",{"type":115,"tag":130,"props":352,"children":354},{"id":353},"_14-storage-access",[355],{"type":120,"value":356},"1.4 Storage access",{"type":115,"tag":116,"props":358,"children":359},{},[360],{"type":120,"value":361},"Verify U-Boot can access the boot storage:",{"type":115,"tag":246,"props":363,"children":365},{"code":364},"U-Boot> mmc info          # eMMC/SD\nU-Boot> sf probe          # SPI NOR\nU-Boot> ubi part nand0    # NAND/UBI\n",[366],{"type":115,"tag":253,"props":367,"children":368},{"__ignoreMap":104},[369],{"type":120,"value":364},{"type":115,"tag":116,"props":371,"children":372},{},[373],{"type":120,"value":374},"Checkpoint: U-Boot can list files on the boot partition or read raw blocks.",{"type":115,"tag":130,"props":376,"children":378},{"id":377},"_15-network-optional-but-valuable",[379],{"type":120,"value":380},"1.5 Network (optional but valuable)",{"type":115,"tag":116,"props":382,"children":383},{},[384],{"type":120,"value":385},"If the board has Ethernet, enable it in U-Boot. TFTP boot dramatically speeds up kernel development:",{"type":115,"tag":246,"props":387,"children":389},{"code":388},"U-Boot> dhcp\nU-Boot> tftp 0x40000000 Image\n",[390],{"type":115,"tag":253,"props":391,"children":392},{"__ignoreMap":104},[393],{"type":120,"value":388},{"type":115,"tag":123,"props":395,"children":397},{"id":396},"stage-2-device-tree",[398],{"type":120,"value":399},"Stage 2: Device tree",{"type":115,"tag":130,"props":401,"children":403},{"id":402},"_21-start-from-the-socs-base-dts",[404],{"type":120,"value":405},"2.1 Start from the SoC's base DTS",{"type":115,"tag":116,"props":407,"children":408},{},[409],{"type":120,"value":410},"The mainline kernel includes DTS files for most SoCs. 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